Overview

RDMA IP Engineering Manager Job at Intel – 4.1 in Austin, TX

Job Description

Job Description



Plans, provides resources for and directs activities in engineering function to meet schedules, standards, and cost. Cultivates and reinforces appropriate group values, norms and behaviors. Identifies and analyzes problems, plans, tasks, and solutions. Provides guidance on employee development, performance, and productivity issues. Plans and schedules daily tasks, uses judgement on a variety of problems requiring deviation from standard practices. Inadequacies and erroneous decisions would cause moderate inconvenience and expense.

Remote Direct Memory Access (RDMA) IP provides high performance low latency connectivity for applications running on private accelerator fabrics to large scale cloud networks. Typical applications include Storage, HPC, and AI/ML. You will manage end-to-end RDMA IP development and delivery to Ethernet sub-system and product integration teams.

Skills:
Commitment to high quality IP standards with minimum exposure to bugs found after integration

Good collaboration skills to interface with planning, architecture, SW, physical design, and system/solution validation stake-holders

Good communication skills to report progress/problems/plans to engineering and management forums

Good understanding of factors that drive power, performance, area trade-offs and data driven decisions

Can do attitude and positive motivational leader

Qualifications

BS/MS in computer or electrical engineering

15+ years of relevant technical experience

5+ years of engineering management experience

Relevant experience building and managing multi-discipline engineering teams including micro-architecture, RTL, FW, and DV

Relevant experience in Ethernet HW development and RDMA or similar technology a must, knowledge of applications using RDMA desired

In-depth knowledge of all aspects of IP development including requirements specification, architecture, design, pre-silicon verification (simulation and emulation), physical design, frontend/backend IP sign-off process, and post-silicon validation

Strong drive to achieve efficient configurable IP that scales features and performance to meet cost sensitive embedded/enterprise and the most demanding cloud networking requirements from one architecture

Relevant knowledge of latest advancements in tools, flows, and methodologies used in IP development

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter….

About Company

Company: Intel – 4.1

Company Location:  Austin, TX

About Intel - 4.1